The present invention relates to a system for generating a clock pulse signal. More particularly, the invention relates to a clock generator system of high reliability which operates to produce a clock pulse signal of high stability (substantially constant frequency).
Digital pulse code modulated (PCM) communication networks consist of a number of remote digital exchanges or "switches" interconnected by digital transmission facilities. Signals transmitted from one switch to another carry digital information at a pulse rate determined by the frequency of the local clock in the originating switch. This digital information is written into the terminating switch's storage register at this same, transmitted frequency. However, this information is read out of the storage register at a rate determined by the terminating switch's local clock. If the clocks of the originating switch and terminating switch operate at different rates, so that information is transmitted and read into a storage register at one rate and read out of this storage register at another rate, it will be seen that this storage register must eventually overflow or exhaust. This impairment, called a "slip", results in either the repetition or deletion of an entire 125 microsecond PCM frame.
It is therefore desirable to operate all clocks of a switched digital network at the same rate. In particular, it is desirable to align the average frequency of the clock pulse signals of all the local, spacially separated clocks of the network. This process of aligning clocks is called "synchronization", a word derived from the Greek words "syn", meaning "together", and "chronos", meaning "time".
Throughout the history of mankind, people have contemplated the nature of space and time and have attempted to create clocks which operate synchronously at remote locations. Countless ingenious methods and devices have been devised through the ages to synchronize remote clocks.
The problems are varied and complex, and these problems have led to solutions which are also varied and complex. Basically, the goal is to establish one extremely stable reference clock at one location and a less stable, yet highly accurate clock at each of the other locations which is capable of synchronizing itself to the reference clock. The reference clock may be an "atomic clock"--for example a rubidium or cesium frequency standard--whereas the remote, slave clocks may operate with a temperature--stabilized, voltage controlled crystal oscillator.
With a synchronized clock system of this type, wherein a plurality of slave clocks are ultimately synchronized to one master reference clock (often via other slave clocks), the following problems must be considered and overcome:
(1) The signal transmitted from the master clock to a slave clock is subject to wander (frequency variation) and jitter (phase variation). Furthermore, the signal may lose its integrity or disappear completely, for example as a result of a natural phenomenon such as a thunderstorm or a manmade break in the signal transmission channel. Thus, the slave clock must be equipped to discern the average frequency of the master clock signal and to detect certain failure conditions of this signal, such as undue wander and jitter or absolute loss of signal, and to take quick remedial action upon detection of failure.
(2) The slave clock must be capable of being maintained on a routine basis, or repaired if a failure occurs, while maintaining a stable, synchronized signal output. These requirements call for a slave clock with at least two, redundant units so that one unit can be removed and maintained or repaired while the other unit continues to operate. However, with two clock units operating simultaneously, there remains the problem of synchronizing these units with each other as well as with the master reference clock. Ideally, it should be possible to switch from one of the two redundant units to the other while maintaining a constant frequency (slip free) and constant phase (glitch free) output signal.
It is therefore known to provide a system comprising a highly stable (and expensive) master clock and a plurality of less stable (and less expensive) slave clocks operating substantially in synchronism with the master clock. It is also known to provide slave clocks in such a system with two or more redundant units. However, it has not, as yet, been possible to provide means at the remote, slave location, for promptly perceiving and detecting certain types of failure of the master clock signal nor has it been possible to switch from one redundant unit at the slave clock site to the other without a discontinuity in frequency and/or phase in the output clock signal produced by this slave clock.
Generally, the detectable failures in the external reference clock signal--that is, the signal from the master clock--are limited to situations where the signal is completely lost or where its frequency changes from its original proper frequency by an amount .DELTA.f for a certain period of time .DELTA.t. In particular, the slave clock is able to measure when .DELTA.f.times..DELTA.t exceeds a prescribed threshold value. As is apparent, failures which commence with a very small change in frequency take considerable time to detect so that the frequencies of the slave clocks, which are locked to the external reference clock signal, will follow the shift in frequency of this reference signal until, ultimately, the slave clock frequency bears no close relationship to the orignal frequency of the master clock.
The second difficulty occurs when one of the two redundant clock units, which is operating "on-line" to produce an output clock signal in response to the incoming reference signal from the master clock, fails and recourse must be had to a second, redundant clock unit. In this case, the second clock unit must immediately be brought on-line so that the system will not lose its synchronism as a result of the failure of the first clock unit. As mentioned above, however, the difficulty arises in that the output of the second clock unit is not normally exactly in phase with that of the first clock unit so that a switch-over from the first to the second redundant clock unit results in a phase discontinuity.